S710D-EST2  GE 数据收发器 数字功能的硬核逻辑实现

概述

S710D数据收发器通过两根多模光纤提供多协议数据的双向传输。数据转换

S710D还具有独特的数据转换功能，可以输入—种数据格式，输出另—种格式。数据格式在安装过程中选择，并且可以通过旋转开关在现场轻松更改。

优越的诊断

SMARTS""诊断技术提供了广泛的系统状态ledl阵列。数据路径的完整性可以用内置的数据传输测试生成器进行测试。不需要连接到外部数据设备。标准特性

支持多协议数据格式，包括RS-232,TTL,RS-422,RS-485，曼彻斯特，Biphase和SensorNet

独特的数据转换功能

用户可配置的数据格式13db光预算

光学自动增益控制智慧诊断

独立和机架配置

S710D-EST2GE数据收发器

S710D-EST2每一路高速收发器包括发送器和接收器两个通道，发送器和接收器都是由物理编码子层(PCS.p场si-cal coding sublayer)与物理介质附

加子层(PMA,physi-cal media additional sublayer)两部分组成。

S710D-EST2包括兼容所支持协议的收发器中的数字功能的硬核逻辑实现，发送通道包括相位补偿FIFO、字节串行器、8B/10B编码器等模块;接收通

道包括字对齐器、速率匹配FIFO,8B/10B解码器、字节解串器、字节排序器、相位补偿FIFO等模块。

S710D-EST2包括/O缓冲器的模拟电路、CDR、串行器/解串器(SER/DES以及用于优化串行数据通道性能的可编程预加重与均衡。

设备收发器通道工作时，FPGA架构中的输出并行数据通过发送器PCS和PMA进行传输，终转化为串行数据发送出去。S710D-EST2接收到的输人

串行数据通过接收器PMA和PCS的处理以串行数据格式传输到FP以架构内部中，进行下一步的处理。

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S710D-EST2  GE 数据收发器 数字功能的硬核逻辑实现

summarize

The S710D data transceiver provides bidirectional transmission of multi-protocol data via two multimode fibers. Data conversion

The S710D also has a unique data conversion function that allows you to input one data format and output another. The data format is selected during installation and can be easily changed in the field with a rotary switch.

Superior diagnosis

SMARTS" diagnostic technology provides a wide array of system state ledl. The integrity of the data path can be tested with the built-in data transfer test generator. No need to connect to external data devices. Standard characteristic

Support for multi-protocol data formats including RS-232,TTL,RS-422,RS-485, Manchester, Biphase, and SensorNet

Unique data conversion capabilities

User configurable data format 13db optical budget

Optical automatic gain control intelligent diagnosis

Standalone and rack configuration

S710D-EST2GE data transceiver

Each S710D-EST2 high-speed transceiver consists of two channels, transmitter and receiver, both of which are attached by physical coding sublayer (PCS.p field si-cal coding sublayer) and physical media

The physi-cal media additional sublayer (PMA) consists of two parts.

S710D-EST2 includes a core logic implementation of the digital function in the transceiver compatible with the supported protocols, and the transmission channel includes the phase compensation FIFO, byte serializer, 8B/10B encoder and other modules; Receive pass

The channel includes word aligner, rate matching FIFO,8B/10B decoder, byte unstring, byte sequencer, phase compensation FIFO and other modules.

The S710D-EST2 includes an analog circuit for the /O buffer, a CDR, a serializer/destringer (SER/DES), and programmable preweight and equalization to optimize the performance of the serial data channel.

When the device transceiver channel works, the output parallel data in the FPGA architecture is transmitted through the sender PCS and PMA, and finally converted into serial data and sent out. S710D-EST2 Indicates the receiver

Serial data is transmitted in serial data format through receiver PMA and PCS processing to the FP architecture for the next step of processing.

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