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Hima-99-2413602 类别: HIMA 数据读取

Hima-99-2413602简短描述,H4136端子外壳中的安全相关继电器放大器,SIL3输入电压48 VDC,开关电压250 VAC/127 VDC,安全隔离。


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Hima-99-2413602 类别: HIMA 数据读取

Hima-99-2413602.jpg

品牌:HIMA

功率:360

型号:Hima-99-2413602

电源电,压:24

电源电流:240


Hima-99-2413602简短描述

H4136端子外壳中的安全相关继电器放大器,SIL3输入电压48 VDC,开关电压250 VAC/127 VDC,安全隔离。


系统的软件设计根据硬件结构的总体划分,也可以分为两大部分来描述。整个系统的运行如图2所示,FPGA和DSP各自的程序独立运行,通过中断信号完成数据的实时交互。FPGA向DSP方向的指令是通过FPGA发送一个EDMA请求,DSP通过响应EDMA请求,建立EDMA通道,开始从FIFO中进行预处理后数据的读取,DSP向FPGA传输数据时,通过向FPGA发送一个中断信号,让其从FIFO中把压缩后的图像数据读出来。


整个系统工作流程可以简单描述如下:系统上电后,首先DSP由flash实现自举,并运行引导程序,之后转入EDMA等待状态,FPGA初始化后等待外部图像采集命令,收到图像采集命令后开始进行图像采集,并对采集到的图像进行预处理,预处理后的图像经过FIFO缓冲,在存储一定量的数据之后,FPGA通过半满信号向DSP发送EDMA请求,等待DSP响应,DSP一旦收到来自FPGA的EDMA请求,立即建立EDMA通道,从FIFO中读取数据到L2存储器,存满一帧图像后DSP开始图像压缩,等待一幅图像压缩完成之后,DSP会向FPGA发送中断信号,FPGA在收到中断信号后开始从FIFO中读取压缩后的图像数据。一帧数据读完后,判断编码信号是否有效,如果有效则按同样的规则对下一帧图像进行压缩,如果无效则通知DSP结束。


厦门雄霸电子商务有限公司的其他产品包括:

ABB: 07AI91 07AC91 07KT97 AI880A CI840A DI810 DO810 EI803FIMDSIO2 PM152 PM861AKO1 SD823等

ICS: T8191 T8403 T8311 T8431 T8461 T8800 T8110B T8293 T8830T8846 T8850等

Hima-99-2413602 类别: HIMA 数据读取

Hima-99-2413602.jpg

Brand :HIMA

Power :360

Model :Hima-99-2413602

Power supply, voltage :24

Power supply current :240


Short description of Hima-99-2413602

Safety-related relay amplifier in H4136 terminal housing, SIL3 input voltage 48 VDC, switching voltage 250 VAC/127 VDC, safe isolation.


The software design of the system can also be divided into two parts according to the overall division of the hardware structure. The operation of the whole system is shown in Figure 2. The programs of FPGA and DSP run independently and complete real-time data interaction through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA, and the DSP establishes an EDMA channel in response to the EDMA request and starts to read the pre-processed data from the FIFO. When the DSP transmits data to the FPGA, it sends an interrupt signal to the FPGA. Let it read the compressed image data out of the FIFO.


The whole system workflow can be simply described as follows: After the system is powered on, the DSP is bootstrapped by flash first, and the boot program is run, and then it is transferred to the EDMA waiting state. After the FPGA is initialized, it waits for the external image acquisition command. After receiving the image acquisition command, the image acquisition begins, and the acquired image is preprocessed. The pre-processed image is buffered by FIFO. After storing a certain amount of data, FPGA sends EDMA request to DSP through half-full signal and waits for DSP response. Once DSP receives EDMA request from FPGA, it immediately establishes EDMA channel and reads data from FIFO to L2 memory. After one frame of image is stored, the DSP starts image compression. After an image compression is completed, the DSP sends an interrupt signal to the FPGA. After receiving the interrupt signal, the FPGA begins to read the compressed image data from the FIFO. After reading a frame of data, the encoded signal is judged whether it is valid. If it is valid, the next frame image is compressed according to the same rules. If it is invalid, the DSP is notified to end.


Other products of Xiamen Xiongba E-commerce Co., LTD include:

ABB: 07AI91 07AC91 07KT97 AI880A CI840A DI810 DO810 EI803FIMDSIO2 PM152 PM861AKO1 SD823 etc

ICS: T8191 T8403 T8311 T8431 T8461 T8800 T8110B T8293 T8830T8846 T8850 etc

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