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ABB IDPG 940128102 数据传输模块

ABB IDPG 940128102  数据传输模块

品牌
ABB
规格
56*56*56
颜色
黑色
特点
模块
加工定制
物料编码
565412
输出频率
230
系统环境
正常
系统能力
操作系统
简单
系统功能
简单
订货号
940128102
重量
1.6kg
产地
瑞士
可售卖地
北京;天津;河北;山西;内蒙古;辽宁;吉


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ABB IDPG 940128102  数据传输模块

ABB IDPG 940128102(3).jpg

IDPG 940128102 ABB所传输的数据可以是源自数据源(例如计算机或键盘)的数字消息。它也可以是模拟信号,例如电话呼叫或视频信号,例如使用脉冲编码调制(PCM)或更高级的信源编码(模数转换和数据压缩)方案被数字化成比特流。这种信源编码和解码是由编解码器设备执行的。整个系统工作流程可以简单描述如下:系统上电后,首先DSP由flash实现自举,并运行引导程序,之后转入EDMA等待状态,FPGA初始化后等待外部图像采集命令,收到图像采集命令后开始进行图像采集,并对采集到的图像进行预处理,预处理后的图像经过FIFO缓冲,在存储一定量的数据之后,FPGA通过半满信号向DSP发送EDMA请求,等待DSP响应,DSP一旦收到来自FPGA的EDMA请求,立即建立EDMA通道,从FIFO中读取数据到L2存储器,存满一帧图像后DSP开始图像压缩,等待一幅图像压缩完成之后,DSP会向FPGA发送中断信号,FPGA在收到中断信号后开始从 FIFO中读取压缩后的图像数据。一帧数据读完后,判断编码信号是否有效,如果有效则按同样的规则对下一帧图像进行压缩,如果无效则通知DSP结束。

ABB IDPG 940128102  数据传输模块

ABB IDPG 940128102(1).jpg


The data transmitted by IDPG 940128102 ABB can be a digital message originating from a data source, such as a computer or keyboard. It can also be an analog signal, such as a telephone call or a video signal, which is digitized into a bit stream using, for example, pulse code modulation (PCM) or a more advanced source coding (analog-to-digital conversion and data compression) scheme. This source coding and decoding is performed by the codec device.The workflow of the whole system can be simply described as follows: after the system is powered on, first, the DSP is bootstrapped by flash, and the boot program is run, and then it turns to the EDMA waiting state. After the FPGA is initialized, it waits for the external image acquisition command, and after receiving the image acquisition command, it starts to acquire the image, and preprocesses the acquired image. The preprocessed image is buffered by FIFO, and after storing a certain amount of data, The FPGA sends an EDMA request to the DSP through a half-full signal, waiting for the DSP to respond. Once the DSP receives the EDMA request from the FPGA, it immediately establishes an EDMA channel, reads data from the FIFO into the L2 memory, and starts image compression after a frame of image is filled. After an image compression is completed, the DSP sends an interrupt signal to the FPGA, and the FPGA starts reading the compressed image data from the FIFO after receiving the interrupt signal. After reading a frame of data, it is judged whether the coded signal is valid. If it is valid, the next frame of image is compressed according to the same rules. If it is invalid, it is notified to DSP to end.

ABB IDPG 940128102  数据传输模块

ABB IDPG 940128102(4).jpg

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